lol. Gulljakten har starta, og det er ikke Sotsij

DB hadde et innlegg fra en av disse "stakkars oss kvinner" om voldtekt.
I leserinnlegg-delen forklarte jeg hvor lei jeg var av gnålet om at "alt" er voldtekt, som om et slag i panna skulle være like mye "voldsoffer" som et knvistikka ransoffer... Og begge deler skulle automatisk gi 150k i erstatning.. For å eksemplisifere nevnte jeg hvor urimelig det var å tro at noen som hadde voldtatt en jente i en bil i 1 time skulle finne på å sleppe henne av på akkurat samme sted og det eneste hun kunne fortelle var at "de snakka utenlandsk..". Sandefjord-saken haddde dukka opp i media dagen før. Artikkelen virka noe inspirert av den episoden, i det minste mtp tidspunktvalg for publisering. Videre nevnte jeg at jenta i det minste skulle ha kudos for å ikke legge skylda på noen faktiske personer i nærmiljøet i sin gulljakt etter 150k. Og at hun faktisk skulle ha litt kudos for sin viten og kalkyle av at politiet må henlegge saken (ingen uskyldige dømt) og at hun deretter kan søke erstatning og likevel høgst trolig få den..

Innlegget fikk meg sperra på hele DB leserinnlegg biten. Litt påfylt av en frem-og-tilbake småkrangel med en mangina, som ikke ble sperret. Nå kan jeg heller ikke lengre kommentere hvor mye ManU suger og hvor lei jeg er av Solskjær-maset .. Ekke mer åpenhet enn i rævhålet mitt, men det visste jeg jo alltid. Gøy å fremprovosere patetismen likevel

I dag popper denne opp i VG (har jo slutta å lese DB nå da, da nivået er meningsløst med mindre man kan kverrulere)
http://www.vg.no/nyheter/innenriks/artikkel.php?artid=10120924


(Med god samvittigheten bruker jeg samme strategi som "motparten", bl.a. manginaen i DB som brukte antall anmeldelser som grunnlag for sitt ståsted. Nemlig å anta at norsk politi alltid har rett når de tar ut tiltale. Dette er seff ikke tilfellet, men hensynet til realiteten og bristen på den må gå begge veier)


Vinden vender...men det vil ta lang tid. Så lang tid at jeg er teoretisk sett pensjonist og derfor ikke vil komme til å skatte med andre midler/smuler enn hva staten har tilgodesett meg av min del av oljen, resten av mitt stusselige liv..
Denne saken er ennå ikke over for statens bekostning. Jenta kan hevde sin rett fremover, påstå seg traumatisert overfor kvinnesakskorrupte sosionomer og psykiatere og motta sin uføretrygd før hun noensinne har gjort et slag for noen og noe som helst.

ok

Patetiske folk i et patetisk land, skildret av en bitte liten patetisk gutt som trolig aldri vil innse egne muligheter og hvor godt han har det. Neppe før han er en gammel -pleietrengende mann som trenger hjelp av patetiske damer som gidder å vaske ræva hans av ren medlidenhet.

Med såkalte skrå øyne på samfunnet og passende kritiske blikk rettet mot den gemene naive hop, så skytes det fortsatt milevis på utsiden av blinken.

dytter opp igjen

Inside the stone bores the hardback biochemistry.

Det norske samfunn kjeder meg også.

Rævhålet ditt ja, virker da ganske åpent det. Sikkert en form for gjennomtrekk som løfter all møkka opp mellom ørene dine...... Kan sikkert medisineres. God bedring.

A rail develops a warm purpose on top of a spigot.

ehm....? altså... nei...hmmm...hæ?

Helt enig.

Enig, samtidig som at der er en herlig underholdende undertone (eller overtone) av håpløshet og resignasjon i innleggene hans.

Just a loner with a boner....

Uenig. Stort sett forutsigbart, liksomprovoserende stoff.
Klarer verken å forholde meg seriøst til det eller la meg provosere. Det fins nok av steder hvor man kan få belyst og diskutert skjevheter og urimeligheter i samfunnet uten å senke seg til pre-pubertalt nivå.

Samtidig så synes duden at det er morsomt nok å bedrive det regelmessig her på terrengsykkel.no av alle ting, så noe må han vel få ut av det.

Abit er vel en umoden utgave av Hvilepuls. Litt morsomt i starten, men etter hvert forutsigbart og kjedelig.

Kanskje vi skulle hatt to nick alle sammen.

Premisset mitt er ekstremt grad av egosentrisme. Norge er anti-altruisme som må renvaskes. Økende for hver generasjon.
Dagens ungdom får ung uføre av årsaker jeg fikk et spark i ræva av min mor for og beskjed om å ikke komme tilbake før sakene var løst.

Med det premisset så dedusere uregelmessighetene så enkelt og faller litt på plass på en ganske kjedelig måte. "Lover og regler skal jo selvfølgelig ikke gjelde meg/min gruppe like mye.... i praksis...men faktum må hvitvaskes, rent teoretisk". Så derfor ender vi opp med "never pratctise what you preach".

Jeg lar meg underholde av å belyse dobbeltmoralen. Påpeker disse offentlige egosentrisme-tilfellene. Angår de meg direkte egentlig. Ikke i alvorlig grad lengre og de som angår meg i mindre alvorlig grad, 99% med skjevt utfall, har jeg i stor grad slutta å bry meg med, akseptert og erkjent at tilfeller som ABB må komme i et slikt samfunn. Det er en praktisk umulighet å innprente "egosentrismen" i alle fra barnsben, og deretter tro at den ideologi ikke vil føre til konflikter. Bortforklaring av slike symptomer må også følge etter. Samfunnet angår meg ikke, jeg driter personlig i det og finner meg subgrupper jeg kan leve med og i, mens jeg venter på at jeg skal kunne komme meg langt vekk. Dermed unngår man også de aller fleste skjevheter derute. Moro og gledelig ? Ikke noe spes, men slikt er en illusjon her til lands for flere grupper. Jeg er ikke engang spesielt forbanna på urettferdigheten og dritten som har hendt meg lengre. Jeg har alltid utsatt meg for den da prinsippet om "ærlighet og rasjonalitet bør alltid føre frem", er noe jeg alltid har visst at ikke fungerer særlig godt her i hverdagslivet. Kostnaden for standhaftigheten er nok at jeg heller ikke bryr meg dritten om dritten som skjer andre, bortsett fra som ren underholdning og aller helst i form av på belyse grunnpremisset, "jeg og meg". På den andre siden, merkelig nok, er jeg en av få som bryr seg umiddelbart når jeg ser dritt hende andre med egne øyne "in real life". Men prøver bevisst å gi fan i det også. Og noe "bedre tilpassa forholdene" har jeg blitt. Saksbehandler sier jeg er blitt veldig flink til å holde meg unna trøbbel. Jeg svarer at "with the good comes the bad" og at jeg også er blitt veldig flink til å gi faen

Når jeg tenker etter, så fant jeg aldri samfunnet særlig prisverdig, særlig altruistisk eller interessant dengang da rulleblad var rent heller. Å ljuge er lett og kjedelig. Typisk norsk å ikke sette pris på et problem og en utfordring. Hadde det vært sulten som drev oss, så fair nuff. Men som eneste nasjon jeg kan komme på i verden, så sloss nordmenn med hverandre ut av kjedsomhet i helgene. Det ranes duplikater av hva man allerede har, for ranets skyld. De øvrige sitter hjemme og spiser seg halvt i hjel, ikke helt i hjel for staten kommer løpende før den bragden er nådd. Våres samfunnsproblemer er luksusproblemer i øvrige verden. Likevel vet vi best og alle andre tar feil.


Hvilepuls og meg ? Må være egosentrisme som slår til igjen. Burde være lett å lese forskjellen mellom linjene om man får øynene bort fra egen nesetipp. Hvilepuls leter fortsatt etter noe å tro på og et håp om at den offentlige ideologi er noe som man skal kunne se i hverdagen. Jeg har for lengst gitt opp og spyr ut galle (eller fakta som det normalt sett bør kalles), ikke for å finne noe å tro på, men for egen underholdnings skyld. Eller som jeg sa til saksbehandler..: Hør her du har 2 valg. Enten avklarer du min situasjon og gir meg en liten mening i å gidde å prøve noe som samfunnet kan få noe godt ut av, eller du lar meg henge for egen jobbs skyld og jeg fortsetter å spre dårlig moral (les: belyse skjevheter, som igjen vil svekke moral hos dem som berøres av forholdene) og drikke opp statens penger. Dessverre er jeg også så glad i fysisk aktivitet, at det siste ikke er noen rask løsning for dem... Overflødig å nevne. Saken er ennå ikke avklart. Snart på 10. år . Jeg begynner å bli redd for at det som engang var prinsipielt, har nå blitt en (u)vane. På den andre siden: Never practise what you preach
Når man er oppvokst fattig og uten noe som helst, har egen kreativitet til å fylle dødtid med, sluttet å begå handlinger man fengsles av og drar fitte likevel, uten spenn, men på utseendet og personlighet. Hvilke pressmidler gjenstår da for saksbehandler, annet enn gleden av å skvise ut gørra av mauren . This is Norway og det er fullstending levelig, gitt at man har hatt det utenomvanligille forut, som jo 99,6% født her, og ikke minst etter 1985, ikke har..

Det er så godt å se ungdommen kanalisere rastløsheten i annet enn "ung uføre", slik som hendte en gang i blant i gamle dager, før internett


Lol. Det fikk meg til å tenke på "saksbehandler", som de siste årene har begynt å mase om at jeg må tenke på pensjonen

tl;dr

Takk.

Mølet som her avleveres er hverken provoserende eller tankevekkende, hvilket jeg antar var trådstarters intensjon.
Aksjon mislykket.

Der poppa lurifax sitt innlegg frem. Der var det jo mye IQ, som vanlig. Godt man er voksen nok til å igge, ikke minst har muligheten.

Otis, du går på igg for iq under 130. Har innsett og erkjent at diskusjoner med dem gir 0 fremdrift og dessuten er utenfor målgruppen min. Man kan ikke senke moralen til noen som ikke har den i utgangspunktet og som aldri vil være i noen posisjon hvor deres mening skulle ha eller få noen betydning likevel.

Siden det kommer fra deg så sier jeg takk professor.

Ser fremdeles ikke hva du skriver (om posten er tiltenkt meg). Ser enda mindre behov for å toggle visning på

Tror vi alle skulle ønske det samme om dine innlegg...
Men det viktigste er jo at ikke du sitter for mye aleine med alle disse tingene.

Jøss, er abit aktiv på åpen linje også?

Hjelp... jeg er ungkar og spiser boksmat, joggu sluntrer jeg unna jobb på Terregnsykkel.no mens min kvinnelig sjef er på jobbreise med stresskoffert også...

Synes det tilogmed det er riktig av gjengvoldtatte kvinner å annmelde det til politiet... finnes det håp for sånne manginaer som meg?

Begynner å bli lang den igge-lista mi nå.

Å trekke inn knivstikking, når realiteten var et slag i panna, i en bistandssak hvor man søker voldsoffererstatning, ja det blir for dumt. Likeså gjengvoldtektsbegrepet.

hva er igge?

Det er ignore listen hans, alle med IQ på under 130 (testet og vedtatt av "the one and only") havner på denne listen.

Det pussige er at "Einstein" faktisk finner det nødvendig å poengtere at han ikke har lest eller sett et innlegg han angivelig har ignorert

Viser bare at selv folk innen Mensa innimellom har mer enn nok med å lokalisere og holde orden på de løse skruene som skramler rundt oppe i topplukket under hår-festet

For å gi mitt siste bidrag til den godeste abit så vil jeg gjerne illustrere hva hans meninger betyr for min del. Det sies at et bilde forteller mer enn 1000 ord. Nesten synd han ikke ser dette

42129J–SAM–12/2013
Description
The Atmel® SAM D20 is a series of low-power microcontrollers using the 32-bit
ARM® Cortex®-M0+ processor, and ranging from 32- to 64-pins with up to 256KB Flash and
32KB of SRAM. The SAM D20 devices operate at a maximum frequency of 48MHz and
reach 2.14 Coremark/MHz. They are designed for simple and intuitive migration with
identical peripheral modules, hex compatible code, identical linear address map and pin
compatible migration paths between all devices in the product series. All devices include
intelligent and flexible peripherals, Atmel Event System for inter-peripheral signaling, and
support for capacitive touch button, slider and wheel user interfaces.
The Atmel SAM D20 devices provide the following features: In-system programmable Flash,
eight-channel Event System, programmable interrupt controller, up to 52 programmable I/O
pins, 32-bit real-time clock and calendar, up to eight 16-bit Timer/Counters (TC). The
timer/counters can be configured to perform frequency and waveform generation, program
execution timing or input capture with time and frequency measurement of digital signals.
The TCs can operate in 8- or 16-bit mode, or be cascaded to form a 32-bit TC. The series
provide up to six Serial Communication Modules (SERCOM) that each can be configured to
act as an USART, UART, SPI and I2C up to 400kHz; up to twenty-channel 350ksps 12-bit
ADC with programmable gain and optional oversampling and decimation supporting up to
16-bit resolution, one 10-bit 350ksps DAC, two analog comparators with window mode,
Peripheral Touch Controller supporting up to 256 buttons, sliders, wheels, and proximity
sensing; programmable Watchdog Timer, brown-out detector and power-on reset, and twopin
Serial Wire Debug (SWD) program and debug interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can
be used as a source for the system clock. Different clock domains can be independently
configured to run at different frequencies while enabling power saving by running each
peripheral at its optimal clock frequency.
The SAM D20 devices have two software-selectable sleep modes, idle and standby. In idle
mode the CPU is stopped while all other functions can be kept running. In standby all clocks
and functions are stopped expect those selected to continue running. The device supports
SleepWalking, which is the module's ability to wake itself up and wake up its own clock, and
hence perform predefined tasks without waking up the CPU. The CPU can then be only
woken on a need basis, e.g. a threshold is crossed or a result is ready. The Event System
supports synchronous and asynchronous events, allowing peripherals to receive, react to
and send events even in standby mode.
The Flash program memory can be reprogrammed in-system through the SWD interface.
The same interface can be used for non-intrusive on-chip debug of application code. A boot
loader running in the device can use any communication interface to download and upgrade
the application program in the Flash memory.
The Atmel SAM D20 devices are supported with a full suite of program and system
development tools, including C compilers, macro assemblers, program
debugger/simulators, programmers and evaluation kits.
Atmel SAM D20J / SAM D20G / SAM D20E
ARM-Based Microcontroller
DATASHEET
Atmel SAM D20 [DATASHEET] 2
42129J–SAM–12/2013
Features
􀁺 Processor
􀁺 ARM Cortex-M0+ CPU running at up to 48MHz
􀁺 Single-cycle hardware multiplier
􀁺 Memories
􀁺 16/32/64/128/256KB in-system self-programmable flash
􀁺 2/4/8/16/32KB SRAM
􀁺 System
􀁺 Power-on reset (POR) and brown-out detection (BOD)
􀁺 Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M)
􀁺 External Interrupt Controller (EIC)
􀁺 16 external interrupts
􀁺 One non-maskable interrupt
􀁺 Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
􀁺 Low Power
􀁺 Idle and standby sleep modes
􀁺 SleepWalking peripherals
􀁺 Peripherals
􀁺 8-channel Event System
􀁺 Up to eight 16-bit Timer/Counters (TC), configurable as either:
􀁺 One 16-bit TC with compare/capture channels
􀁺 One 8-bit TC with compare/capture channels
􀁺 One 32-bit TC with compare/capture channels, by using two TCs
􀁺 32-bit Real Time Counter (RTC) with clock/calendar function
􀁺 Watchdog Timer (WDT)
􀁺 CRC-32 generator
􀁺 Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either:
􀁺 USART with full-duplex and single-wire half-duplex configuration
􀁺 I2C up to 400kHz
􀁺 SPI
􀁺 One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels
􀁺 Differential and single-ended channels
􀁺 1/2x to 16x gain stage
􀁺 Automatic offset and gain error compensation
􀁺 Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
􀁺 10-bit, 350ksps Digital-to-Analog Converter (DAC)
􀁺 Two Analog Comparators with window compare function
􀁺 Peripheral Touch Controller (PTC)
􀁺 256-Channel capacitive touch and proximity sensing
􀁺 I/O
􀁺 Up to 52 programmable I/O pins
􀁺 Packages
􀁺 64-pin TQFP, QFN
􀁺 48-pin TQFP, QFN
􀁺 32-pin TQFP, QFN
􀁺 Operating Voltage
􀁺 1.62V – 3.63V
􀁺 Power Consumption
􀁺 Down to 70μA/MHz in active mode
􀁺 Down to 8μA running the Peripheral Touch Controller
Atmel SAM D20 [DATASHEET] 3
42129J–SAM–12/2013
1. Configuration Summary
SAM D20J SAM D20G SAM D20E
Number of pins 64 48 32
General Purpose I/O-pins (GPIOs) 52 38 26
Flash 256/128/64/32/16KB 256/128/64/32/16KB 256/128/64/32/16KB
SRAM 32/16/8/4/2KB 32/16/8/4/2KB 32/16/8/4/2KB
Maximum CPU frequency 48MHz
Event System channels 8 8 8
Timer Counter (TC) 8 6 6
Waveform output channels for TC 2 2 2
Serial Communication Interface
(SERCOM) 6 6 4
Analog-to-Digital Converter (ADC)
channels 20 14 10
Analog comparators 2 2 2
Digital-to-Analog Converter (DAC)
channels 1 1 1
Real-Time Counter (RTC) Yes Yes Yes
RTC alarms 1 1 1
RTC compare values 1 32-bit value or
2 16-bit values
1 32-bit value or
2 16-bit values
1 32-bit value or
2 16-bit values
External Interrupt lines 16 16 16
Peripheral Touch Controller (PTC) X
and Y lines 16x16 12x10 10x6
Packages QFN
TQFP
QFN
TQFP
QFN
TQFP
Oscillators
32.768kHz crystal oscillator (XOSC32K)
0.4-32MHz crystal oscillator (XOSC)
32.768kHzinternal oscillator (OSC32K)
32kHz ultra-low-power internal oscillator (OSCULP32K)
8MHz high-accuracy internal oscillator (OSC8M)
48MHz Digital Frequency Locked Loop (DFLL48M)
SW Debug Interface Yes Yes Yes
Watchdog Timer (WDT) Yes Yes Yes
Atmel SAM D20 [DATASHEET] 4
42129J–SAM–12/2013
2. Ordering Information
2.1 SAM D20E
ATSAMD 20 E 14 A ‐ M U T
Product Family
ATSAMD = General Purpose Microcontroller
Product Series
20 = Cortex M0+ CPU, General Feature Set
Flash Memory
18 = 256KB
17 = 128KB
16 = 64KB
15 = 32KB
14 = 16KB
Device Variant
A = Default Variant
Pin Count
E = 32 Pins
G = 48 Pins
J = 64 Pins
Package Carrier
No character = Tray (Default)
T = Tape and Reel
Package Grade
Package Type
A = TQFP
M = QFN
C = UBGA
U = WLCSP
U = ‐40 ‐ 85°C Matte Sn Plating
Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type
ATSAMD20E14A-AU
16K 2K
TQFP32
Tray
ATSAMD20E14A-AUT Tape & Reel
ATSAMD20E14A-MU
QFN32
Tray
ATSAMD20E14A-MUT Tape & Reel
ATSAMD20E15A-AU
32K 4K
TQFP32
Tray
ATSAMD20E15A-AUT Tape & Reel
ATSAMD20E15A-MU
QFN32
Tray
ATSAMD20E15A-MUT Tape & Reel
ATSAMD20E16A-AU
64K 8K
TQFP32
Tray
ATSAMD20E16A-AUT Tape & Reel
ATSAMD20E16A-MU
QFN32
Tray
ATSAMD20E16A-MUT Tape & Reel
ATSAMD20E17A-AU
128K 16K
TQFP32
Tray
ATSAMD20E17A-AUT Tape & Reel
ATSAMD20E17A-MU
QFN32
Tray
ATSAMD20E17A-MUT Tape & Reel
Atmel SAM D20 [DATASHEET] 5
42129J–SAM–12/2013
2.2 SAM D20G
ATSAMD20E18A-AU
256K 32K
TQFP32
Tray
ATSAMD20E18A-AUT Tape & Reel
ATSAMD20E18A-MU
QFN32
Tray
ATSAMD20E18A-MUT Tape & Reel
Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type
Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type
ATSAMD20G14A-AU
16K 2K
TQFP48
Tray
ATSAMD20G14A-AUT Tape & Reel
ATSAMD20G14A-MU
QFN48
Tray
ATSAMD20G14A-MUT Tape & Reel
ATSAMD20G15A-AU
32K 4K
TQFP48
Tray
ATSAMD20G15A-AUT Tape & Reel
ATSAMD20G15A-MU
QFN48
Tray
ATSAMD20G15A-MUT Tape & Reel
ATSAMD20G16A-AU
64K 8K
TQFP48
Tray
ATSAMD20G16A-AUT Tape & Reel
ATSAMD20G16A-MU
QFN48
Tray
ATSAMD20G16A-MUT Tape & Reel
ATSAMD20G17A-AU
128K 16K
TQFP48
Tray
ATSAMD20G17A-AUT Tape & Reel
ATSAMD20G17A-MU
QFN48
Tray
ATSAMD20G17A-MUT Tape & Reel
ATSAMD20G18A-AU
256K 32K
TQFP48
Tray
ATSAMD20G18A-AUT Tape & Reel
ATSAMD20G18A-MU
QFN48
Tray
ATSAMD20G18A-MUT Tape & Reel
Atmel SAM D20 [DATASHEET] 6
42129J–SAM–12/2013
2.3 SAM D20J
Ordering Code FLASH (bytes) SRAM (bytes) Package Carrier Type
ATSAMD20J14A-AU
16K 2K
TQFP64
Tray
ATSAMD20J14A-AUT Tape & Reel
ATSAMD20J14A-MU
QFN64
Tray
ATSAMD20J14A-MUT Tape & Reel
ATSAMD20J15A-AU
32K 4K
TQFP64
Tray
ATSAMD20J15A-AUT Tape & Reel
ATSAMD20J15A-MU
QFN64
Tray
ATSAMD20J15A-MUT Tape & Reel
ATSAMD20J16A-AU
64K 8K
TQFP64
Tray
ATSAMD20J16A-AUT Tape & Reel
ATSAMD20J16A-MU
QFN64
Tray
ATSAMD20J16A-MUT Tape & Reel
ATSAMD20J17A-AU
128K 16K
TQFP64
Tray
ATSAMD20J17A-AUT Tape & Reel
ATSAMD20J17A-MU
QFN64
Tray
ATSAMD20J17A-MUT Tape & Reel
ATSAMD20J18A-AU
256K 32K
TQFP64
Tray
ATSAMD20J18A-AUT Tape & Reel
ATSAMD20J18A-MU
QFN64
Tray
ATSAMD20J18A-MUT Tape & Reel
Atmel SAM D20 [DATASHEET] 7
42129J–SAM–12/2013
3. Block Diagram
Notes: 1. Some products have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC signals. Refer to “Configuration Summary” on
page 3 for details.
6 x SERCOM
8 x Timer Counter
REAL TIME
COUNTER
AHB-APB
BRIDGE C
M
HIGH SPEED S
BUS MATRIX
PORT
PORT
WATCHDOG
TIMER
SERIAL
SWDIO WIRE
NVM
CONTROLLER
256/128/64/32/16KB
FLASH
S
ARM CORTEX-M0+
PROCESSOR
Fmax 48MHz
SWCLK
DEVICE
SERVICE
UNIT
AHB-APB
BRIDGE A
ADC
AIN[19:0]
VREFA
AIN[3:0]
S
32/16/8/4/2KB
RAM
M
RESET
CONTROLLER
SLEEP
CONTROLLER
CLOCK
CONTROLLER
POWER MANAGER
RESET
8 x TIMER COUNTER
EVENT SYSTEM
S
6 x SERCOM
2 ANALOG
COMPARATORS
SYSTEM CONTROLLER
XOUT
XIN
XOUT32
XIN32
OSCULP32K
OSC32K
OSC8M
DFLL48M
BOD33
XOSC32K
XOSC
VREF
GENERIC CLOCK
X[15:0]
Y[15:0]
PERIPHERAL
TOUCH
CONTROLLER
PERIPHERAL
ACCESS CONTROLLER
AHB-APB
BRIDGE B
VREFP
VOUT
DAC
EXTERNAL INTERRUPT
CONTROLLER
PERIPHERAL
ACCESS CONTROLLER
PERIPHERAL
ACCESS CONTROLLER
EXTINT[15:0]
NMI
GCLK_IO[7:0]
S
PIN[3:0]
WO[1:0]
VREFB
(See Note1)
CMP1:0]
ARM SINGLE CYCLE IOBUS
CONTROLLER
Atmel SAM D20 [DATASHEET] 8
42129J–SAM–12/2013
4. Pinout
4.1 SAM D20J
PA00 1
PA01 2
PA02 3
PA03 4
PB04 5
PB05 6
GNDANA 7
VDDANA 8
PB06 9
PB07 10
PB08 11
PB09 12
PA04 13
PA05 14
PA06 15
PA07 16
PA08 17
PA09 18
PA10 19
PA11 20
VDDIO 21
GND 22
PB10 23
PB11 24
PB12 25
PB13 26
PB14 27
PB15 28
PA12 29
PA13 30
PA14 31
PA15 32
48 VDDIO
47 GND
46 PA25
45 PA24
44 PA23
43 PA22
42 PA21
41 PA20
40 PB17
39 PB16
38 PA19
37 PA18
36 PA17
35 PA16
34 VDDIO
33 GND
49 PB22
50 PB23
51 PA27
52 RESET
53 PA28
54 GND
55 VDDCORE
56 VDDIN
57 PA30
58 PA31
59 PB30
60 PB31
61 PB00
62 PB01
63 PB02
PB03 64 DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel SAM D20 [DATASHEET] 9
42129J–SAM–12/2013
4.2 SAM D20G
PA21
PA00 1
PA01 2
PA02 3
PA03 4
GNDANA 5
VDDANA 6
PB08 7
PB09 8
PA04 9
PA05 10
PA06 11
PA07 12
PA08 13
PA09 14
PA10 15
PA11 16
VDDIO 17
GND 18
PB10 19
PB11 20
PA12 21
PA13 22
PA14 23
PA15 24
36 VDDIO
35 GND
34 PA25
33 PA24
32 PA23
31 PA22
30
29 PA20
28 PA19
27 PA18
26 PA17
25 PA16
37 PB22
38 PB23
39 PA27
40 RESET
41 PA28
42 GND
43 VDDCORE
44 VDDIN
45 PA30
46 PA31
47 PB02
48 PB03
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel SAM D20 [DATASHEET] 10
42129J–SAM–12/2013
4.3 SAM D20E
PA00 1
PA01 2
PA02 3
PA03 4
PA04 5
PA05 6
PA06 7
PA07 8
VDDANA 9
GND 10
PA08 11
PA09 12
PA10 13
PA11 14
PA14 15
PA15 16
24 PA25
23 PA24
22 PA23
21 PA22
20 PA19
19 PA18
18 PA17
17 PA16
25 PA27
26 RESET
27 PA28
28 GND
29 VDDCORE
30 VDDIN
31 PA30
32 PA31
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Atmel SAM D20 [DATASHEET] 11
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5. I/O Multiplexing and Considerations
5.1 Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the
peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable
bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0-31) in the PORT must be written
to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in
the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT. Refer to “PORT” on page 279 for details on how to
configure the I/O multiplexing.
Table 5-1 describes the peripheral signals multiplexed to the PORT I/O pins.
Table 5-1. PORT Function Multiplexing
Pin
I/O
Pin Supply
Pin
Type
A B(1) C D E F G H
SAM
D20E
SAM
D20G
SAM
D20J EIC REF ADC AC PTC DAC SERCOM(2) TC(3) AC/GCLK
1 1 1 PA00 VDDANA EXTINT[0] SERCOM1/
PAD[0]
TC2/
WO[0]
2 2 2 PA01 VDDANA EXTINT[1] SERCOM1/
PAD[1]
TC2/
WO[1]
3 3 3 PA02 VDDANA EXTINT[2] AIN[0] Y[0] VOUT
4 4 4 PA03 VDDANA EXTINT[3] ADC/VREFA
DAC/VREFA AIN[1] Y[1]
5 PB04 VDDANA EXTINT[4] AIN[12] Y[10]
6 PB05 VDDANA EXTINT[5] AIN[13] Y[11]
9 PB06 VDDANA EXTINT[6] AIN[14] Y[12]
10 PB07 VDDANA EXTINT[7] AIN[15] Y[13]
7 11 PB08 VDDANA EXTINT[8] AIN[2] Y[14] SERCOM4/
PAD[0]
TC4/
WO[0]
8 12 PB09 VDDANA EXTINT[9] AIN[3] Y[15] SERCOM4/
PAD[1]
TC4/
WO[1]
5 9 13 PA04 VDDANA EXTINT[4] ADC/
VREFB AIN[4] AIN[0] Y[2] SERCOM0/
PAD[0]
TC0/
WO[0]
6 10 14 PA05 VDDANA EXTINT[5] AIN[5] AIN[1] Y[3] SERCOM0/
PAD[1]
TC0/
WO[1]
7 11 15 PA06 VDDANA EXTINT[6] AIN[6] AIN[2] Y[4] SERCOM0/
PAD[2]
TC1/
WO[0]
8 12 16 PA07 VDDANA EXTINT[7] AIN[7] AIN[3] Y[5] SERCOM0/
PAD[3]
TC1/
WO[1]
11 13 17 PA08 VDDIO I2C NMI AIN[16] X[0] SERCOM0/
PAD[0]
SERCOM2/
PAD[0]
TC0/
WO[0]
12 14 18 PA09 VDDIO I2C EXTINT[9] AIN[17] X[1] SERCOM0/
PAD[1]
SERCOM2/
PAD[1]
TC0/
WO[1]
13 15 19 PA10 VDDIO EXTINT[10] AIN[18] X[2] SERCOM0/
PAD[2]
SERCOM2/
PAD[2]
TC1/
WO[0] GCLK_O[4]
14 16 20 PA11 VDDIO EXTINT[11] AIN[19] X[3] SERCOM0/
PAD[3]
SERCOM2/
PAD[3]
TC1/
WO[1] GCLK_IO[5]
19 23 PB10 VDDIO EXTINT[10] SERCOM4/
PAD[2]
TC5/
WO[0] GCLK_IO[4]
20 24 PB11 VDDIO EXTINT[11] SERCOM4/
PAD[3]
TC5/
WO[1] GCLK_IO[5]
25 PB12 VDDIO I2C EXTINT[12] X[12] SERCOM4/
PAD[0]
TC4/
WO[0] GCLK_IO[6]
26 PB13 VDDIO I2C EXTINT[13] X[13] SERCOM4/
PAD[1]
TC4/
WO[1] GCLK_IO[7]
27 PB14 VDDIO EXTINT[14] X[14] SERCOM4/
PAD[2]
TC5/
WO[0] GCLK_IO[0]
Atmel SAM D20 [DATASHEET] 12
42129J–SAM–12/2013
Note: 1. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin.
28 PB15 VDDIO EXTINT[15] X[15] SERCOM4/
PAD[3]
TC5/
WO[1] GCLK_IO[1]
21 29 PA12 VDDIO I2C EXTINT[12] SERCOM2/
PAD[0]
SERCOM4/
PAD[0]
TC2/
WO[0] AC/CMP[0]
22 30 PA13 VDDIO I2C EXTINT[13] SERCOM2/
PAD[1]
SERCOM4/
PAD[1]
TC2/
WO[1] AC/CMP[1]
15 23 31 PA14 VDDIO EXTINT[14] SERCOM2/
PAD[2]
SERCOM4/
PAD[2]
TC3/
WO[0] GCLK_IO[0]
16 24 32 PA15 VDDIO EXTINT[15] SERCOM2/
PAD[3]
SERCOM4/
PAD[3]
TC3/
WO[1] GCLK_IO[1]
17 25 35 PA16 VDDIO I2C EXTINT[0] X[4] SERCOM1/
PAD[0]
SERCOM3/
PAD[0]
TC2/
WO[0] GCLK_IO[2]
18 26 36 PA17 VDDIO I2C EXTINT[1] X[5] SERCOM1/
PAD[1]
SERCOM3/
PAD[1]
TC2/
WO[1] GCLK_IO[3]
19 27 37 PA18 VDDIO EXTINT[2] X[6] SERCOM1/
PAD[2]
SERCOM3/
PAD[2]
TC3/
WO[0] AC/CMP[0]
20 28 38 PA19 VDDIO EXTINT[3] X[7] SERCOM1/
PAD[3]
SERCOM3/
PAD[3]
TC3/
WO[1] AC/CMP[1]
39 PB16 VDDIO I2C EXTINT[0] SERCOM5/
PAD[0]
TC6/
WO[0] GCLK_IO[2]
40 PB17 VDDIO I2C EXTINT[1] SERCOM5/
PAD[1]
TC6/
WO[1] GCLK_IO[3]
29 41 PA20 VDDIO EXTINT[4] X[8] SERCOM5/
PAD[2]
SERCOM3/
PAD[2]
TC7/
WO[0] GCLK_IO[4]
30 42 PA21 VDDIO EXTINT[5] X[9] SERCOM5/
PAD[3]
SERCOM3/
PAD[3]
TC7/
WO[1] GCLK_IO[5]
21 31 43 PA22 VDDIO I2C EXTINT[6] X[10] SERCOM3/
PAD[0]
SERCOM5/
PAD[0]
TC4/
WO[0] GCLK_IO[6]
22 32 44 PA23 VDDIO I2C EXTINT[7] X[11] SERCOM3/
PAD[1]
SERCOM5/
PAD[1]
TC4/
WO[1] GCLK_IO[7]
23 33 45 PA24 VDDIO EXTINT[12] SERCOM3/
PAD[2]
SERCOM5/
PAD[2]
TC5/
WO[0]
24 34 46 PA25 VDDIO EXTINT[13] SERCOM3/
PAD[3]
SERCOM5/
PAD[3]
TC5/
WO[1]
37 49 PB22 VDDIO EXTINT[6] SERCOM5/
PAD[2]
TC7/
WO[0] GCLK_IO[0]
38 50 PB23 VDDIO EXTINT[7] SERCOM5/
PAD[3]
TC7/
WO[1] GCLK_IO[1]
25 39 51 PA27 VDDIO EXTINT[15] GCLK_IO[0]
27 41 53 PA28 VDDIO EXTINT[8] GCLK_IO[0]
31 45 57 PA30 VDDIO EXTINT[10] SERCOM1/
PAD[2]
TC1/
WO[0] SWCLK GCLK_IO[0]
32 46 58 PA31 VDDIO EXTINT[11] SERCOM1/
PAD[3]
TC1/
WO[1] SWDIO(4)
59 PB30 VDDIO I2C EXTINT[14] SERCOM5/
PAD[0]
TC0/
WO[0]
60 PB31 VDDIO I2C EXTINT[15] SERCOM5/
PAD[1]
TC0/
WO[1]
61 PB00 VDDANA EXTINT[0] AIN[8] Y[6] SERCOM5/
PAD[2]
TC7/
WO[0]
62 PB01 VDDANA EXTINT[1] AIN[9] Y[7] SERCOM5/
PAD[3]
TC7/
WO[1]
47 63 PB02 VDDANA EXTINT[2] AIN[10] Y[8] SERCOM5/
PAD[0]
TC6/
WO[0]
48 64 PB03 VDDANA EXTINT[3] AIN[11] Y[9] SERCOM5/
PAD[1]
TC6/
WO[1]
Table 5-1. PORT Function Multiplexing (Continued)
Pin
I/O
Pin Supply
Pin
Type
A B(1) C D E F G H
SAM
D20E
SAM
D20G
SAM
D20J EIC REF ADC AC PTC DAC SERCOM(2) TC(3) AC/GCLK
Atmel SAM D20 [DATASHEET] 13
42129J–SAM–12/2013
2. Only some pins can be used in SERCOM I2C mode. See the Type column for using a SERCOM pin in I2C mode. Refer to the “I2C Pins” on page 571 for details
on the I2C pin characteristics
3. Note that TC6 and TC7 are not supported on the SAM D20G. Refer to “Configuration Summary” on page 3 for details.
4. This function is only activated in the presence of a debugger
5.2 Other Functions
5.2.1 Oscillator Pinout
The oscillators are not mapped to the normal PORT functions and their multiplexing are controlled by registers in the
System Controller (SYSCTRL). Refer to “SYSCTRL – System Controller” on page 128 for more information.
5.2.2 Serial Wire Debug Interface Pinout
After reset, SWCLK functionality is selected for pin PA30 to allow for debugger probe detection. The application software
can switch the SWCLK functionality of PA30 to GPIO (or other peripherals) during runtime. PA31, by default, is configured
like other normal I/O pins and will automatically switch to SWDIO function when a debugger cold-plugging or hotplugging
is detected. When the device is put in debug mode, application software accesses to PA30 and PA31 PORT
registers are ignored.
Refer to “DSU – Device Service Unit” on page 37 for more information.
Oscillator Supply Signal I/O Pin
XOSC VDDIO
XIN PA14
XOUT PA15
XOSC32K VDDANA
XIN32 PA00
XOUT32 PA01
Signal Supply I/O Pin
SWCLK VDDIO PA30
SWDIO VDDIO PA31
Atmel SAM D20 [DATASHEET] 14
42129J–SAM–12/2013
6. Signal Descriptions List
The following table gives details on signal names classified by peripheral.
Signal Name Function Type Active Level
Analog Comparators - AC
AIN[3:0] AC Analog Inputs Analog
CMP[1:0] AC Comparator Outputs Digital
Analog Digital Converter - ADC
AIN[19:0] ADC Analog Inputs Analog
VREFP ADC Voltage External Reference Analog
Digital Analog Converter - DAC
VOUT DAC Voltage output Analog
VREFP DAC Voltage External Reference Analog
External Interrupt Controller
EXTINT[15:0] External Interrupts Input
NMI External Non-Maskable Interrupt Input
Generic Clock Generator - GCLK
GCLK_IO[7:0] Generic Clock (source clock or generic clock generator output) I/O
Power Manager - PM
RESET Reset Input Low
Serial Communication Interface - SERCOMx
PAD[3:0] SERCOM I/O Pads I/O
System Control - SYSCTRL
XIN Crystal Input Analog/ Digital
XIN32 32kHz Crystal Input Analog/ Digital
XOUT Crystal Output Analog
XOUT32 32kHz Crystal Output Analog
Timer Counter - TCx
WO[1:0] Waveform Outputs Output Low
Peripheral Touch Controller - PTC
X[15:0] PTC Input Analog
Y[15:0] PTC Input Analog
General Purpose I/O - PORT
PA25 - PA00 Parallel I/O Controller I/O Port A I/O
Atmel SAM D20 [DATASHEET] 15
42129J–SAM–12/2013
PA28 - PA27 Parallel I/O Controller I/O Port A I/O
PA31 - PA30 Parallel I/O Controller I/O Port A I/O
PB17 - PB00 Parallel I/O Controller I/O Port B I/O
PB23 - PB22 Parallel I/O Controller I/O Port B I/O
PB31 - PB30 Parallel I/O Controller I/O Port B I/O
Signal Name Function Type Active Level
Atmel SAM D20 [DATASHEET] 16
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7. Power Supply and Start-Up Considerations
7.1 Power Domain Overview
7.2 Power Supply Considerations
7.2.1 Power Supplies
The Atmel® SAM D20 has several different power supply pins:
􀁺 VDDIO: Powers I/O lines, OSC8M and XOSC. Voltage is 1.62V to 3.63V.
􀁺 VDDIN: Powers I/O lines and the internal regulator. Voltage is 1.62V to 3.63V.
􀁺 VDDANA: Powers I/O lines and the ADC, AC, DAC, PTC, OSCULP32K, OSC32K, XOSC32K. Voltage is 1.62V to
3.63V.
􀁺 VDDCORE: Internal regulated voltage output. Powers the core, memories and peripherals. Voltage is 1.2V.
The same voltage must be applied to both VDDIN, VDDIO and VDDANA. This common voltage is referred to as VDD in
the datasheet.
The ground pins, GND, are common to VDDCORE, VDDIO and VDDIN. The ground pin for VDDANA is GNDANA.
VOLTAGE
REGULATOR
VDDIN
VDDCORE
GND
ADC
AC
DAC
PTC
XOSC32K
OSC32K
VDDANA
GNDANA
PA[7:2]
PB[9:0]
PA[1:0]
Digital Logic
(CPU, peripherals)
DFLL48M
VDDIO
OSC8M
XOSC
OSCULP32K
PA[31:16]
PB[31:10]
PA[15:14]
BOD33
POR
BOD12 PA[13:8]
Atmel SAM D20 [DATASHEET] 17
42129J–SAM–12/2013
For decoupling recommendations for the different power supplies, refer to the schematic checklist.
Refer to “Schematic Checklist” on page 609 for details.
7.2.2 Voltage Regulator
The voltage regulator has two different modes:
􀁺 Normal mode: To be used when the CPU and peripherals are running
􀁺 Low Power (LP) mode: To be used when the regulator draws small static current. It can be used in standby mode
7.2.3 Typical Powering Schematics
The SAM D20 uses a single supply from 1.62V to 3.63V.
The following figure shows the recommended power supply connection.
Figure 7-1. Power Supply Connection
7.2.4 Power-Up Sequence
7.2.4.1 Minimum Rise Rate
The integrated power-on reset (POR) circuitry monitoring the VDDANA power supply requires a minimum rise rate. Refer
to the “Electrical Characteristics” on page 563 for details.
7.2.4.2 Maximum Rise Rate
The rise rate of the power supply must not exceed the values described in Electrical Characteristics. Refer to the
“Electrical Characteristics” on page 563 for details.
(1.62V — 3.63V)
Main Supply VDDIO
VDDANA
VDDIN
VDDCORE
GND
GNDANA
SAM D20
Atmel SAM D20 [DATASHEET] 18
42129J–SAM–12/2013
7.3 Power-Up
This section summarizes the power-up sequence of the SAM D20. The behavior after power-up is controlled by the
Power Manager. Refer to “PM – Power Manager” on page 101 for details.
7.3.1 Starting of Clocks
After power-up, the device is set to its initial state and kept in reset, until the power has stabilized throughout the device.
Once the power has stabilized, the device will use a 1MHz clock. This clock is derived from the 8MHz Internal Oscillator
(OSC8M), which is divided by eight and used as a clock source for generic clock generator 0. Generic clock generator 0
is the main clock for the Power Manager (PM).
Some synchronous system clocks are active, allowing software execution.
Refer to the “Clock Mask Register” section in “PM – Power Manager” on page 101 for the list of default peripheral clocks
running. Synchronous system clocks that are running are by default not divided and receive a 1MHz clock through
generic clock generator 0. Other generic clocks are disabled except GCLK_WDT, which is used by the Watchdog Timer
(WDT).
7.3.2 I/O Pins
After power-up, the I/O pins are tri-stated.
7.3.3 Fetching of Initial Instructions
After reset has been released, the CPU starts fetching PC and SP values from the reset address, which is 0x00000000.
This address points to the first executable address in the internal flash. The code read from the internal flash is free to
configure the clock system and clock sources. Refer to “PM – Power Manager” on page 101, “GCLK – Generic Clock
Controller” on page 79 and “SYSCTRL – System Controller” on page 128 for details. Refer to the ARM Architecture
Reference Manual for more information on CPU startup (http://www.arm.com).
7.4 Power-On Reset and Brown-Out Detector
The SAM D20 embeds three features to monitor, warn and/or reset the device:
􀁺 POR: Power-on reset on VDDANA
􀁺 BOD33: Brown-out detector on VDDANA
􀁺 BOD12: Voltage Regulator Internal Brown-out detector on VDDCORE. The Voltage Regulator Internal BOD is
calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration should
not be changed if the user row is written to assure the correct behavior of the BOD12.
7.4.1 Power-On Reset on VDDANA
POR monitors VDDANA. It is always activated and monitors voltage at startup and also during all the sleep modes. If
VDDANA goes below the threshold voltage, the entire chip is reset.
7.4.2 Brown-Out Detector on VDDANA
BOD33 monitors VDDANA. Refer to “SYSCTRL – System Controller” on page 128 for details.
7.4.3 Brown-Out Detector on VDDCORE
Once the device has started up, BOD12 monitors the internal VDDCORE.
Atmel SAM D20 [DATASHEET] 19
42129J–SAM–12/2013
8. Product Mapping
Figure 8-1. SAM D20 Product Mapping
This figure represents the full configuration of the Atmel® SAM D20 with maximum flash and SRAM capabilities and a full
set of peripherals. Refer to the “Configuration Summary” on page 3 for details.
Code
SRAM
Undefined
Peripherals
Reserved
Undefined
Global Memory Space
0x00000000
0x20000000
0x20008000
0x40000000
0x43000000
0x60000000
0x60000200
0xFFFFFFFF
Internal SRAM
SRAM
0x20000000
0x20008000
AHB-APB
Bridge A
AHB-APB
Bridge B
AHB-APB
Bridge C
Peripherals
0x40000000
0x41000000
0x42000000
0x42FFFFFF
Reserved
PAC0
PM
SYSCTRL
GCLK
WDT
RTC
EIC
AHB-APB Bridge A
0x40000000
0x40000400
0x40000800
0x40000C00
0x40001000
0x40001400
0x40001800
0x40FFFFFF
0x40001C00
AHB-APB Bridge B
Reserved
PAC1
DSU
NVMCTRL
PORT
0x41000000
0x41002000
0x41004000
0x41004400
0x41FFFFFF
0x41004800
Internal flash
Code
0x00000000
0x00040000
0x1FFFFFFF
Reserved
SERCOM5
PAC2
EVSYS
SERCOM0
SERCOM1
SERCOM2
SERCOM3
SERCOM4
AHB-APB Bridge C
TC7
TC0
TC1
TC2
TC3
TC4
TC5
TC6
ADC
AC
0x42000000
0x42000400
0x42000800
0x42000C00
0x42001000
0x42001400
0x42001800
0x42002000
0x42001C00
0x42003000
0x42003400
0x42003800
0x42003C00
0x42004000
0x42004400
0x42004800
Reserved
0x42FFFFFF
DAC
0x42004C00
0x42002400
0x42002800
0x42002C00
PTC
0x42005000
Reserved
System
0xE0000000
SCS
Reserved
Reserved
ROM Table
Reserved
System
0xE0000000
0xE000E000
0xE000F000
0xE00FF000
0xE0100000
0xFFFFFFFF
Atmel SAM D20 [DATASHEET] 20
42129J–SAM–12/2013
9. Memories
9.1 Embedded Memories
􀁺 Internal high-speed flash
􀁺 Internal high-speed RAM, single-cycle access at full speed
􀁺 Dedicated flash area for EEPROM emulation
9.2 Physical Memory Map
The High-Speed bus is implemented as a Bus Matrix. Refer to “High-Speed Bus Matrix” on page 26 for details. All High-
Speed bus addresses are fixed, and they are never remapped. The 32-bit physical address space is mapped as follows:
Table 9-1. SAM D20 Physical Memory Map(1)
Note: 1. x = G, J or E. Refer to “Ordering Information” on page 4 for details.
Table 9-2. Flash Memory Parameters(1)
Notes: 1. x = G, J or E. Refer to “Ordering Information” on page 4 for details.
2. The number of pages (NVMP) and page size (PSZ) can be read from the NVM Pages and Page Size bits in the NVM Parameter register in the
NVMCTRL (PARAM.NVMP and PARAM.PSZ, respectively). Refer to PARAM for details.
Memory Start address
Size
SAMD20x18 SAMD20x17 SAMD20x16 SAMD20x15 SAMD20x14
Embedded Flash 0x00000000 256KB 128KB 64KB 32KB 16KB
Embedded SRAM 0x20000000 32KB 16KB 8KB 4KB 2KB
AHB-APB Bridge A 0x40000000 64KB 64KB 64KB 64KB 64KB
AHB-APB Bridge B 0x41000000 64KB 64KB 64KB 64KB 64KB
AHB-APB Bridge C 0x42000000 64KB 64KB 64KB 64KB 64KB
Device Flash Size Number of Pages (NVMP) Page Size (PSZ) Row Size
ATSAMD20x18 256KB 4096 64 bytes 4 pages = 256 bytes
ATSAMD20x17 128KB 2048 64 bytes 4 pages = 256 bytes
ATSAMD20x16 64KB 1024 64 bytes 4 pages = 256 bytes
ATSAMD20x15 32KB 512 64 bytes 4 pages = 256 bytes
ATSAMD20x14 16KB 256 64 bytes 4 pages = 256 bytes
Atmel SAM D20 [DATASHEET] 21
42129J–SAM–12/2013
Figure 9-1. Calibration and Auxiliary space
The values from the automatic calibration row is loaded into their respective registers on startup.
0x00800000
AUX0 offset address
Automatic calibration
row Calibration and auxiliary
space address offset
AUX0 – NVM User
Row
AUX1
0x00804000
0x00806000 AUX1 offset address
0x00806000
Area 3 offset address
Area 1: Reserved (64 bits)
Area 2: Device configuration
area (64 bits)
Area 1 address offset
Area 2 offset address
Area 3: Reserved
(128bits)
Area 4: Software
calibration area (256bits)
0x00806008
0x00806010
0x00806020 Area 4 offset address
AUX1
0x00806040
0x00000000
NVM base address
+ NVM size
NVM main address
space
NVM Base Address
Calibration and
0x00800000 auxiliary space
NVM base address +
0x00800000
Atmel SAM D20 [DATASHEET] 22
42129J–SAM–12/2013
9.3 Non-Volatile Memory (NVM) User Row Mapping
The NVM User Row contains calibration data that are automatically read at device power on.
The NVM User Row can be read at address 0x804000.
To write the NVM User Row refer to “NVMCTRL – Non-Volatile Memory Controller” on page 257.
Note that when writing to the User Row the values will only be loaded at device reset.
Table 9-3. NVM User Row Mapping
Notes: 1. On rev C: Bit 40 is “Reserved” and Default value = 1.
2. On rev C: Bit 41 is “Reserved” and Default value = 1.
Bit Position Name Description
2:0 BOOTPROT Used to select one of eight different bootloader sizes. Refer to “NVMCTRL –
Non-Volatile Memory Controller” on page 257. Default value = 7.
3 Reserved
6:4 EEPROM
Used to select one of eight different EEPROM area sizes. Refer to
“NVMCTRL – Non-Volatile Memory Controller” on page 257. Default
value = 7.
7 Reserved
13:8 BOD33 Level BOD33 Threshold Level (BOD33.LEVEL) at power on. Refer to BOD33
register. Default value = 7.
14 BOD33 Enable BOD33 Enable at power on. Refer to BOD33 register. Default value = 1.
16:15 BOD33 Action BOD33 Action at power on. Refer to BOD33 register. Default value = 1.
24:17 Reserved Voltage Regulator Internal BOD(BOD12) configuration. These bits are written
in production and must not be changed. Default value = 0x70.
25 WDT Enable WDT Enable at power on. Refer to WDT CTRL register. Default value = 0.
26 WDT Always-On WDT Always-On at power on. Refer to WDT CTRL register. Default value = 0.
30:27 WDT Period WDT Period at power on. Refer to WDT CONFIG register. Default
value = 0xB.
34:31 WDT Window WDT Window mode time-out at power on. Refer to WDT CONFIG register.
Default value = 0xB.
38:35 WDT EWOFFSET WDT Early Warning Interrupt Time Offset at power on. Refer to WDT
EWCTRL register. Default value = 0xB.
39 WDT WEN WDT Timer Window Mode Enable at power on. Refer to WDT CTRL register.
Default value = 0.
40(1) BOD33 Hysteresis BOD33 Hysteresis configuration at power on. Refer to BOD33 register. Default
value = 0.
41(2) Reserved Voltage Regulator Internal BOD(BOD12) configuration. This bit is written in
production and must not be changed. Default value = 0.
47:42 Reserved
63:48 LOCK NVM Region Lock Bits. Refer to “NVMCTRL – Non-Volatile Memory
Controller” on page 257. Default value = 0xFFFF.
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9.4 NVM Software Calibration Area Mapping
The NVM Software Calibration Area contains calibration data that are measured and written during production test.
These calibration values should be read by the application software and written back to the corresponding register.
The NVM Software Calibration Area can be read at address 0x806020.
The NVM Software Calibration Area can not be written.
Table 9-4. NVM Software Calibration Area Mapping
9.5 Serial Number
Each device has a unique 128-bit serial number which is a concatenation of four 32-bit words contained at the following
addresses:
Word 0: 0x0080A00C
Word 1: 0x0080A040
Word 2: 0x0080A044
Word 3: 0x0080A048
The uniqueness of the serial number is guaranteed only when using all 128 bits.
Bit Position Name Description
2:0 Reserved
14:3 Reserved
26:15 Reserved
34:27 ADC LINEARITY ADC Linearity Calibration. Should be written to CALIB register.
37:35 ADC BIASCAL ADC Bias Calibration. Should be written to CALIB register.
44:38 OSC32K CAL OSC32KCalibration. Should be written to OSC32K register.
57:45 Reserved
63:58 DFLL48M COARSE CAL DFLL48M Coarse calibration value. Should be written to the DFLLVAL
register.
73:64 DFLL48M FINE CAL DFLL48M Fine calibration value. Should be written to the DFLLVAL register.
127:74 Reserved
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10. Processor and Architecture
10.1 Cortex-M0+ Processor
The Atmel® SAM D20 implements the ARM® Cortex®-M0+ processor, which is based on the ARMv6 architecture and
Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 processor, and
upward compatible with the Cortex-M3 and Cortex-M4 processors. The ARM Cortex-M0+ implemented is revision r0p1.
For more information, refer to www.arm.com.
10.1.1 Cortex-M0+ Configuration
Note: 1. All software run in privileged mode only
The ARM Cortex-M0+ processor has two bus interfaces:
􀁺 Single 32-bit AMBA® 3 AHB-Lite™ system interface that provides connections to peripherals and all system
memory, including flash and RAM
􀁺 Single 32-bit I/O port bus interfacing to the PORT with one-cycle loads and stores
10.1.2 Cortex-M0+ Peripherals
􀁺 System Control Space (SCS)
􀁺 The processor provides debug through registers in the SCS. Refer to the Cortex-M0+ Technical Reference
Manual for details (www.arm.com).
􀁺 System Timer (SysTick)
􀁺 The System Timer is a 24-bit timer that extends the functionality of both the processor and the NVIC. Refer
to the Cortex-M0+ Technical Reference Manual for details (www.arm.com).
Feature Configurable Option SAM D20 Configuration
Interrupts External interrupts 0-32 32
Data endianness Little-endian or big-endian Little-endian
SysTick timer Present or absent Present
Number of watchpoint comparators 0, 1, 2 2
Number of breakpoint comparators 0, 1, 2, 3, 4 4
Halting debug support Present or absent Present
Multiplier Fast or small Fast (single cycle)
Single-cycle I/O port Present or absent Present
Wake-up interrupt controller Supported or not supported Not supported
Vector Table Offset Register Present or absent Present
Unprivileged/Privileged support Present or absent Absent
Memory Protection Unit Not present or 8-region Not present
Reset all registers Present or absent Absent(1)
Instruction fetch width 16-bit only or mostly 32-bit 32-bit
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􀁺 Nested Vectored Interrupt Controller (NVIC)
􀁺 External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the
priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low
latency interrupt processing and efficient processing of late arriving interrupts. Refer to “Nested Vector
Interrupt Controller” on page 25 and the Cortex-M0+ Technical Reference Manual for details
(www.arm.com).
􀁺 System Control Block (SCB)
􀁺 The System Control Block provides system implementation information, and system control. This includes
configuration, control, and reporting of the system exceptions. Refer to the Cortex-M0+ Devices Generic
User Guide for details (www.arm.com).
10.1.3 Cortex-M0+ Address Map
Table 10-1. Cortex-M0+ Address Map
10.1.4 I/O Interface
10.1.4.1 Overview
Because accesses to the AMBA AHB-Lite and the single-cycle I/O interface can be made concurrently, the Cortex-M0+
processor can fetch the next instructions while accessing the I/Os. This enables single-cycle I/O accesses to be
sustained for as long as needed.
10.1.4.2 Description
Direct access to PORT registers.
10.2 Nested Vector Interrupt Controller
10.2.1 Overview
The Nested Vectored Interrupt Controller (NVIC) in the SAM D20 supports 32 interrupt lines with four different priority
levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (www.arm.com).
10.2.2 Interrupt Line Mapping
Each of the 32 interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral can
have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register. The
interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by
writing a one to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and disabled by
writing a one to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request
is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt
requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An
interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers
(SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt
enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority
field for each interrupt.
Address Peripheral
0xE000E000 System Control Space (SCS)
0xE000E010 System Timer (SysTick)
0xE000E100 Nested Vectored Interrupt Controller (NVIC)
0xE000ED00 System Control Block (SCB)
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10.3 High-Speed Bus Matrix
10.3.1 Features
The High-Speed Bus Matrix includes these features:
􀁺 Symmetric crossbar bus switch implementation
􀁺 Allows concurrent accesses from different masters to different slaves
􀁺 32-bit data bus
􀁺 Operation at a one-to-one clock frequency with the bus masters
Peripheral Source NVIC Line
EIC NMI – External Interrupt Controller Non Maskable Interrupt NMI
PM – Power Manager 0
SYSCTRL – System Controller 1
WDT – Watchdog Timer 2
RTC – Real Time Counter 3
EIC – External Interrupt Controller 4
NVMCTRL – Non-Volatile Memory Controller 5
EVSYS – Event System 6
SERCOM0 – Serial Communication Interface 0 7
SERCOM1 – Serial Communication Interface 1 8
SERCOM2 – Serial Communication Interface 2 9
SERCOM3 – Serial Communication Interface 3 10
SERCOM4 – Serial Communication Interface 4 11
SERCOM5 – Serial Communication Interface 5 12
TC0 – Timer/Counter 0 13
TC1 – Timer/Counter 1 14
TC2 – Timer/Counter 2 15
TC3 – Timer/Counter 3 16
TC4 – Timer/Counter 4 17
TC5 – Timer/Counter 5 18
TC6 – Timer/Counter 6 19
TC7 – Timer/Counter 7 20
ADC – Analog-to-Digital Converter 21
AC – Analog Comparator 22
DAC – Digital-to-Analog Converter 23
PTC – Peripheral Touch Controller 24
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10.3.2 Configuration
CM0+ 0
DSU 1
High-Speed Bus
Slaves
Internal Flash
0
AHB-APB bridge A
1
AHB-APB bridge B
2
AHB-APB bridge C
3
Internal SRAM
4
High-Speed Bus
Masters
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10.4 AHB-APB Bridge
The AHB-APB bridge is an AHB slave, providing an interface between the high-speed AHB domain and the low-power
APB domain. It is used to provide access to the programmable control registers of peripherals (see “Product Mapping” on
page 19).
to operate the AHB-APB bridge, the clock (CLK_HPBx_AHB) must be enabled. See “PM – Power Manager” on page 101
for details.
10.5 PAC – Peripheral Access Controller
10.5.1 Overview
There is one PAC associated with each AHB-APB bridge. The PAC can provide write protection for registers of each
peripheral connected on the same bridge.
The PAC peripheral bus clock (CLK_PACx_APB) is enabled by default, and can be enabled and disabled in the Power
Manager. Refer to “PM – Power Manager” on page 101 for details. The PAC will continue to operate in any sleep mode
where the selected clock source is running.
Write-protection does not apply for debugger access. When the debugger makes an access to a peripheral, writeprotection
is ignored so that the debugger can update the register.
Write-protect registers allow the user to disable a selected peripheral’s write-protection without doing a read-modify-write
operation. These registers are mapped into two I/O memory locations, one for clearing and one for setting the register
bits. Writing a one to a bit in the Write Protect Clear register (WPCLR) will clear the corresponding bit in both registers
(WPCLR and WPSET) and disable the write-protection for the corresponding peripheral, while writing a one to a bit in the
Write Protect Set (WPSET) register will set the corresponding bit in both registers (WPCLR and WPSET) and enable the
write-protection for the corresponding peripheral. Both registers (WPCLR and WPSET) will return the same value when
read.
If a peripheral is write-protected, and if a write access is performed, data will not be written, and the peripheral will return
an access error (CPU exception).
The PAC also offers a safety feature for correct program execution, with a CPU exception generated on double writeprotection
or double unprotection of a peripheral. If a peripheral n is write-protected and a write to one in WPSET[n] is
detected, the PAC returns an error. This can be used to ensure that the application follows the intended program flow by
always following a write-protect with an unprotect, and vice versa. However, in applications where a write-protected
peripheral is used in several contexts, e.g., interrupts, care should be taken so that either the interrupt can not happen
while the main application or other interrupt levels manipulate the write-protection status, or when the interrupt handler
needs to unprotect the peripheral, based on the current protection status, by reading WPSET.
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10.6 Register Description
Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and
the 8-bit halves of a 16-bit register can be accessed directly.
Refer to “Product Mapping” on page 19 for PAC locations.
10.6.1 Write Protect Clear
Name: WPCLR
Offset: 0x00
Reset: 0x00000000
Property: -
􀁺 Bits 31:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
􀁺 Bits 6:1 – EIC, RTC, WDT, GCLK, SYSCTRL, PM: Write Protect Disable
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bits for the corresponding peripherals.
􀁺 Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit 31 30 29 28 27 26 25 24
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EIC RTC WDT GCLK SYSCTRL PM
Access R R/W R/W R/W R/W R/W R/W R
Reset 0 0 0 0 0 0 0 0
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10.6.2 Write Protect Set
Name: WPSET
Offset: 0x04
Reset: 0x00000000
Property: -
􀁺 Bits 31:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
􀁺 Bits 6:1 – EIC, RTC, WDT, GCLK, SYSCTRL, PM: Write Protect Enable
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write Protect bit for the corresponding peripherals.
􀁺 Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit 31 30 29 28 27 26 25 24
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EIC RTC WDT GCLK SYSCTRL PM
Access R R/W R/W R/W R/W R/W R/W R
Reset 0 0 0 0 0 0 0 0
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10.6.3 PAC1 Register Description
Write Protect Clear
Name: WPCLR
Offset: 0x00
Reset: 0x00000002
Property: -
􀁺 Bits 31:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
􀁺 Bits 3:1 – PORT, NVMCTRL, DSU: Write Protect
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
􀁺 Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit 31 30 29 28 27 26 25 24
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PORT NVMCTRL DSU
Access R R R R R/W R/W R/W R
Reset 0 0 0 0 0 0 1 0
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Write Protect Set
Name: WPSET
Offset: 0x04
Reset: 0x00000002
Property: -
􀁺 Bits 31:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
􀁺 Bits 3:1 – PORT, NVMCTRL, DSU: Write Protect
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write Protect bit for the corresponding peripherals.
􀁺 Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit 31 30 29 28 27 26 25 24
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
PORT NVMCTRL DSU
Access R R R R R/W R/W R/W R
Reset 0 0 0 0 0 0 1 0
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10.6.4 PAC2 Register Description
Write Protect Clear
Name: WPCLR
Offset: 0x00
Reset: 0x00100000
Property: -
􀁺 Bits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
reset value when this register is written. These bits will always return reset value when read.
􀁺 Bits 19:1 – PTC, DAC, AC, ADC, TC7, TC6, TC5, TC4, TC3, TC2, TC1, TC0, SERCOM5, SERCOM4,
SERCOM3, SERCOM2, SERCOM1, SERCOM0, EVSYS: Write Protect
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
􀁺 Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit 31 30 29 28 27 26 25 24
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
PTC DAC AC ADC
Access R R R R R/W R/W R/W R/W
Reset 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS
Access R/W R/W R/W R/W R/W R/W R/W R
Reset 0 0 0 0 0 0 0 0
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Write Protect Set
Name: WPSET
Offset: 0x04
Reset: 0x00100000
Property: -
􀁺 Bits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
reset value when this register is written. These bits will always return reset value when read.
􀁺 Bits 19:1 – PTC, DAC, AC, ADC, TC7, TC6, TC5, TC4, TC3, TC2, TC1, TC0, SERCOM5, SERCOM4,
SERCOM3, SERCOM2, SERCOM1, SERCOM0, EVSYS: Write Protect Enable
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write Protect bit for the corresponding peripherals.
􀁺 Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
Bit 31 30 29 28 27 26 25 24
Access R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
PTC DAC AC ADC
Access R R R R R/W R/W R/W R/W
Reset 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8
TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS
Access R/W R/W R/W R/W R/W R/W R/W R
Reset 0 0 0 0 0 0 0 0
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11. Peripherals Configuration Overview
The following table shows an overview of all the peripherals in the device. The IRQ Line column shows the interrupt
mapping, as described in “Nested Vector Interrupt Controller” on page 25.
The AHB and APB clock indexes correspond to the bit in the AHBMASK and APBMASK (x = A, B or C) registers in the
Power Manager, while the Enabled at Reset column shows whether the peripheral clock is enabled at reset (Y) or not
(N). Refer to the Power Manager AHBMASK, APBAMASK, APBBMASK and APBCMASK registers for details.
The Generic Clock Index column corresponds to the value of the Generic Clock Selection ID bits in the Generic Clock
Control register (CLKCTRL.ID) i